Electrically Erasable Programmable Read Only Memory (EEPROM) permits stored data to be retained even if power to the memory is removed. An EEPROM cell stores data either by storing electrical charge in an electrically isolated floating gate of a field effect transistor (FET), or by storing electrical charge in a dielectric layer underlying a control gate of a FET. The stored electrical charge controls the threshold of the FET, thereby controlling the memory state of the EEPROM cell.
In the past, many EEPROM devices have utilized either Fowler-Nordheim tunneling or channel hot electron injection at the drain side of the memory cell for programming. However, as EEPROM devices are scaled down in size, channel hot electron injection becomes disadvantageous in that the high power needed to trigger injection becomes increasingly difficult to generate on-chip from a high voltage generator or from a charge pumping circuit. Moreover, as device sizes are scaled down, the relative area of the charge pumps and the corresponding high-voltage switching circuitry increases with respect to the useful area of the memory chip. Fowler-Nordheim tunneling, on the other hand, is limited by tunnel-oxide scaling limits and by the very high voltages needed on chip for the tunneling to occur, both of which compromise device reliability and process scalability.
Source-side hot carrier injection has emerged as a viable alternative to Fowler-Nordheim tunneling and to channel hot electron injection for EEPROM programming, particularly as device sizes are scaled down, due in part to its unique combination at moderate voltages of relatively low power consumption and high programming speed. To program an EEPROM cell using source side hot carrier injection, a select gate is formed overlying a portion of the channel region adjacent to the source region. The select gate is electrically isolated from a control gate formed adjacent to the drain region. During programming, an electric field is established in the channel region so that charge carriers originating in the source region are accelerated across the channel region before being injected into a floating gate or a dielectric layer located below the control gate. The select gate controls the channel current. Independent of the select gate, the control gate controls the vertical electric field for hot carrier injection. Thus, programming with source side hot carrier injection is more power efficient than the conventional drain side hot carrier injection, and is suitable for low voltage and low power applications.
FIGS. 1-2 illustrate one particular EEPROM device which is known to the art. The device 101 shown therein comprises a first polysilicon layer in which are defined first 103 and second 105 floating gates, and a second polysilicon layer in which are defined a control gate 107 and first 109 and second 111 program gates. The cell boundary 113 of an individual memory cell in the device is indicated by a dashed line.
FIG. 2 depicts a cross-sectional view of the EEPROM device of FIG. 1 as taken along LINE 2-2, and also indicates the conventional voltages utilized in these devices. As seen therein, the EEPROM device has a multibit non-volatile memory cell structure comprising (a) a semiconductor substrate 113 of a first conductivity type, (b) first 115 and a second 117 junction regions which are of a second conductivity type and which form a part of a first and a second bitline, (c) first 103 and second 105 floating gates, and (d) a control gate 107 which is part of a wordline running perpendicular to said first and second bitline. The read, write and erase functions for each cell in this device utilize two polysilicon layers, and each memory cell has two locations for storing a charge representing at least one bit.
While devices of the type shown in FIG. 1 have certain notable advantages, they also suffer from certain infirmities. In particular, the fabrication processes currently known to the art for making such devices are not commercially feasible. Also, devices of the type shown in FIG. 1 are found to have high wordline and bitline sheet resistances. There is thus a need in the art for a fabrication process that overcomes these infirmities. There is also a need in the art for a nonvolatile memory device that exhibits lower wordline and bitline sheet resistances. These and other needs may be met by the devices and methodologies described herein.